// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:10 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  pcs_raw_creg_ctl.v
//
//  Control regsiter Interface and muxing between PARA and JTAG CREG interfaces
//
//  Original Author: Chris Jones
//  Current Owner:   Ameer Youssef
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2013 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: ameer $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_creg_ctl.v $
//    $DateTime: 2014/09/26 10:11:27 $
//    $Revision: #12 $
//
////////////////////////////////////////////////////////////////////////////// 


`include "dwc_e12mp_phy_x4_ns_jtag_macros.v"
`include "dwc_e12mp_phy_x4_ns_cr_macros.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_creg_ctl (
input  wire                       cr_para_sel_i,

// CR Parallel Interface
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr_para_addr,
input  wire                       cr_para_wr_en,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_para_wr_data,
input  wire                       cr_para_rd_en,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_para_rd_data,
output wire                       cr_para_ack,

// JTAG Register interface
input  wire                       jtag_rst,
input  wire                       jtag_clk,
input  wire                       jtag_clk_n,                      
input  wire                       jtag_capture,
input  wire                       jtag_shift,
input  wire                       jtag_update,
input  wire                       jtag_ser_in,
input  wire                       jtag_crsel_sel,
output wire                       jtag_crsel_tdo,
                 
// Internal CREG interface
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_addr,
output wire                       cr_wr_en,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_wr_data,
output wire                       cr_rd_en,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_rd_data,
input  wire                       cr_ack
);

// Wires for JTAG CREG module.
wire  [`DWC_E12MP_X4NS_CR_ADDR_RANGE]       cr_jtag_addr;
wire                              cr_jtag_wr_en;
wire  [`DWC_E12MP_X4NS_CR_DATA_RANGE]       cr_jtag_wr_data;
wire                              cr_jtag_rd_en;
wire  [`DWC_E12MP_X4NS_CR_DATA_RANGE]       cr_jtag_rd_data;
wire                              cr_jtag_ack;

// Instantiate the JTAG registers (CR_SEL & ALU)
dwc_e12mp_phy_x4_ns_creg_jtag creg_jtag (
  // JTAG interface
  .jtag_rst              (jtag_rst),
  .jtag_clk              (jtag_clk),
  .jtag_clk_n            (jtag_clk_n),
  .jtag_capture          (jtag_capture),
  .jtag_shift            (jtag_shift),
  .jtag_update           (jtag_update),
  .jtag_ser_in           (jtag_ser_in),
  .jtag_crsel_sel        (jtag_crsel_sel),
  .jtag_crsel_tdo        (jtag_crsel_tdo),
  
  // Interface back to creg_ctl
  .cr_jtag_addr          (cr_jtag_addr),
  .cr_jtag_wr_en         (cr_jtag_wr_en),
  .cr_jtag_wr_data       (cr_jtag_wr_data),
  .cr_jtag_rd_en         (cr_jtag_rd_en),
  .cr_jtag_rd_data       (cr_jtag_rd_data),
  .cr_jtag_ack           (cr_jtag_ack)
); 

// MUX the CREG bus between JTAG and PARA
// Replace with gen_mux'es
//assign cr_addr    = (cr_para_sel_i) ? cr_para_addr    : cr_jtag_addr; 
//assign cr_wr_en   = (cr_para_sel_i) ? cr_para_wr_en   : cr_jtag_wr_en; 
//assign cr_wr_data = (cr_para_sel_i) ? cr_para_wr_data : cr_jtag_wr_data; 
//assign cr_rd_en   = (cr_para_sel_i) ? cr_para_rd_en   : cr_jtag_rd_en; 

// addr
dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(`DWC_E12MP_X4NS_CR_ADDR_LEN)) cr_addr_mux (
  .out (cr_addr),
  .sel (cr_para_sel_i),
  .d0  (cr_jtag_addr),
  .d1  (cr_para_addr)
);
// wr_data
dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(`DWC_E12MP_X4NS_CR_DATA_LEN)) cr_wr_data_mux (
  .out (cr_wr_data),
  .sel (cr_para_sel_i),
  .d0  (cr_jtag_wr_data),
  .d1  (cr_para_wr_data)
);
// wr_en
dwc_e12mp_phy_x4_ns_gen_mux cr_wr_en_mux (
  .out (cr_wr_en),
  .sel (cr_para_sel_i),
  .d0  (cr_jtag_wr_en),
  .d1  (cr_para_wr_en)
);
// rd_en
dwc_e12mp_phy_x4_ns_gen_mux cr_rd_en_mux (
  .out (cr_rd_en),
  .sel (cr_para_sel_i),
  .d0  (cr_jtag_rd_en),
  .d1  (cr_para_rd_en)
);

// Replace with gen_mux'es
//assign cr_para_rd_data = cr_rd_data;
//assign cr_para_ack     = cr_ack;
//assign cr_jtag_rd_data = (cr_para_sel_i) ? {`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}} : cr_rd_data;
//assign cr_jtag_ack     = (cr_para_sel_i) ? 1'b0 : cr_ack;

// cr_para_rd_data
dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(`DWC_E12MP_X4NS_CR_DATA_LEN)) cr_para_rd_data_mux (
  .out (cr_para_rd_data),
  .sel (cr_para_sel_i),
  .d0  ({`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}}),
  .d1  (cr_rd_data)
);

// cr_para_ack
dwc_e12mp_phy_x4_ns_gen_mux cr_para_ack_mux (
  .out (cr_para_ack),
  .sel (cr_para_sel_i),
  .d0  (1'b0),
  .d1  (cr_ack)
);

// cr_jtag_rd_data
dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(`DWC_E12MP_X4NS_CR_DATA_LEN)) cr_jtag_rd_data_mux (
  .out (cr_jtag_rd_data),
  .sel (cr_para_sel_i),
  .d0  (cr_rd_data),
  .d1  ({`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}})
);

// cr_jtag_ack
dwc_e12mp_phy_x4_ns_gen_mux cr_jtag_ack_mux (
  .out (cr_jtag_ack),
  .sel (cr_para_sel_i),
  .d0  (cr_ack),
  .d1  (1'b0)
);

endmodule


